S1OF2 – One of two analog signals selector

Block SymbolLicensing group: ADVANCED

Function Description
The S1OF2 block assesses the validity of two input signals u1 and u2 separately. The validation method is equal to the method used in the SAI block. If the signal u1 (or u2) is marked invalid, the output E1 (or E2) is set to on and the error code is sent to the iE1 (or iE2) output. The S1OF2 block also evaluates the difference between the two input signals. The internal flag D is set to on if the differences $| u1 - u2 |$ in the last nd samples exceed the given limit, which is given by the following inequation

| u1 - u2 | > pdev \frac{vmax - vmin}{100},

where vmin and vmax are the minimal and maximal limits of the inputs u1 and u2 and pdev is the allowed percentage difference with respect to the overall range of the input signals. The value of the output y depends on the validity of the input signals (flags E1 and E2) and the internal difference flag D as follows:

(i) If $E1 = off$ and $E2 = off$ and $D = off$: , then the output y depends on the mode parameter: $y = \{\begin{matrix} \frac{u1 + u2}{2}, & f o r mode = 1, \\ min (u1, u2), & f o r mode = 2, \\ max (u1, u2), & f o r mode = 3, \end{matrix}$
and the output E is set to off unless set to on earlier.
(ii) If $E1 = off$ and $E2 = off$ and $D = on$: , then $y = sv$ and $E = on$ .
(iii) If $E1 = on$ and $E2 = off$ ( $E1 = off$ and $E2 = on$ ): , then $y = u2$ ( $y = u1$ ) and the output E is set to off unless set to on earlier.
(iv) If $E1 = on$ and $E2 = on$: , then $y = sv$ and $E = on$ .

The input R resets the inner error flags Fl–F4 (see the SAI block) and the D flag. For the input R set permanently to on, the invalidity indicator E1 (E2) is set to on for only one cycle period whenever some invalidity condition is fulfilled. On the other hand, for $R = 0$ , the output E1 (E2) is set to on and remains true until the reset (R: off $\to$ on). A similar rule holds for the E output. For the input R set permanently to on, the E output is set to on for only one cycle period whenever a rising edge occurs in the internal D flag ( $D = off \to on$ ). On the other hand, for $R = 0$ , the output E is set to on and remains true until the reset (rising edge R: off $\to$ on). The output W is set to on only in the (iii) or (iv) cases, i.e. at least one input signal is invalid.

Inputs

u1	First analog input of the block	Double (F64)
u2	Second analog input of the block	Double (F64)
sv	Substitute value for an error case, i.e. $E = on$	Double (F64)
HF1	Hardware error flag for signal u1	Bool
	off .. The input module of the signal works normally on ... Hardware error of the input module occurred
HF2	Hardware error flag for signal u2	Bool
	off .. The input module of the signal works normally on ... Hardware error of the input module occurred
R	Reset inner error flags of the input signals u1 and u2	Bool

Outputs

y	Analog output of the block	Double (F64)
E	Output signal invalidity indicator	Bool
	off .. Signal is valid on ... Signal is invalid
E1	Invalidity indicator for input u1	Bool
	off .. Signal is valid on ... Signal is invalid, $y = u2$
E2	Invalidity indicator for input u2	Bool
	off .. Signal is valid on ... Signal is invalid, $y = u1$
iE1	Reason of input u1 invalidity	Long (I32)
	0 .... Signal valid 1 .... Signal out of range 2 .... Signal varies too little 3 .... Signal varies too little and signal out of range 4 .... Signal varies too much 5 .... Signal varies too much and signal out of range 6 .... Signal varies too much and too little 7 .... Signal varies too much and too little and signal out of range 8 .... Hardware error
iE2	Reason of input u2 invalidity, see the iE1 output	Long (I32)
W	Warning flag (invalid input signal)	Bool
	off .. Both input signals u1 and u2 are valid on ... At least one of the input signals is invalid

Parameters

nb	Number of samples which are not included in the validity assessment of the signals u1 and u2 after initialization of the block $⊙$ 10	Long (I32)
nc	Number of samples for invariability testing (see the SAI block, condition F2) $⊙$ 10	Long (I32)
nbits	Number of A/D converter bits (source of the signals u1 and u2) $⊙$ 12	Long (I32)
nr	Number of samples for variability testing (see the SAI block, condition F3) $⊙$ 10	Long (I32)
prate	Maximum allowed percentage change of the input u1 (u2) within the last nr samples (with respect to the overall range of the input signals $vmax - vmin$ , see the SAI block) $⊙$ 10.0	Double (F64)
nv	Number of samples for out-of-range testing (see the SAI block, condition F4) $⊙$ 1	Long (I32)
vmin	Lower limit for the input signals u1 and u2 $⊙$ -1.0	Double (F64)
vmax	Upper limit for the input signals u1 and u2 $⊙$ 1.0	Double (F64)
nd	Number of samples for deviation testing (inner flag D; D is always off for $nd = 0$ ) $⊙$ 5	Long (I32)
pdev	Maximum allowed percentage deviation of the inputs u1 and u2 with respect to the overall range of the input signals $vmax - vmin$ $⊙$ 10.0	Double (F64)
mode	Defines how to compute the output signal y when both input signals are valid ( $E1 = off$ , $E2 = off$ and $D = off$ ) $⊙$ 1	Long (I32)
	1 .... Average, $y = \frac{u1 + u2}{2}$ 2 .... Minimum, $y = min (u1, u2)$ 3 .... Maximum, $y = max (u1, u2)$

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